The present disclosure relates to field effect transistors and, more specifically, to gate-all-around field effect transistors (GAAFETs) and method of forming these GAAFETs.
More specifically, integrated circuit design decisions are often driven by device scalability. For example, size scaling of planar field effect transistors (FETs) resulted in the development of planar FETs with relatively short channel lengths; however, the smaller channel lengths resulted in a corresponding increase in short channel effects and a decrease in drive current. To decrease short channel effects and increase drive current, different types of multi-gate non-planar field effect transistors (MUGFETs), such as fin-type FETs (FINFETs) (also referred to herein as a dual gate FETs) and tri-gate FETs, were developed. A FINFET is a MUGFET comprising a relatively thin semiconductor body (also referred to as a semiconductor fin) having a channel region positioned laterally between source/drain regions. A gate stack is adjacent to the top surface and opposing sides of the semiconductor body at the channel region. Since the semiconductor body of this FINFET is relatively thin, the FINFET essentially exhibits only two-dimensional field effects. That is, since its semiconductor body is relatively thin, a FINFET will exhibit field effects at the opposing sides of the channel region, but any field effects exhibited at the top surface of the channel region will be negligible. A tri-gate FET is a MUGFET that is similar in structure to a FINFET, except it has a relative wide semiconductor body and, thus, it exhibits three-dimensional field effects. That is, since its semiconductor body is relative wide, a tri-gate FET will exhibit field effects at the opposing sides and top surface of the channel region. Oftentimes, multiple semiconductor bodies and/or multiple gate stacks will be incorporated into a given MUGFET structure in order to increase drive current as well as device density. However, with conventional methods of forming such MUGFETS, further size scaling causes increases in gate resistance and gate-to-source/drain contact capacitance, which negatively impact device performance. Therefore, there is a need in the art for improved field effect transistor (FET) structures and methods of forming the structures that allow for further size scaling, while avoiding corresponding increases in gate resistance and gate-to-source/drain contact capacitance.